Embodiments of the inventive concept relate to a memory module and a semiconductor memory system, and more particularly, to a memory module and a semiconductor memory system capable of improving signal integrity.
Semiconductor memory devices used in electronic systems have been developed with increased capacity and operating speeds. Dynamic random access memory (DRAM), for example, has come into widespread use in computer systems, such as personal computers (PCs) or servers. In order to increase the performance and capacity of a semiconductor memory device, multiple semiconductor memories are mounted in a memory module, which is installed in a computer system.
Examples of DRAM include synchronous semiconductor memory devices, e.g., synchronous dynamic random access memory (SDRAM), which operate in synchronization with a system clock signal. Examples of SDRAM include double-data-rate (DDR) SDRAM that delivers data in synchronization with rising and falling edges of a system clock signal. DDR SDRAM has evolved into DDR2 SDRAM, DDR3 SDRAM, etc., the performances of which are respectively improved in terms of operating speeds. Such semiconductor memory devices have different operating characteristics, and thus, a memory system needs a memory controller suitable for each semiconductor memory device.
FIG. 1 is a block diagram of a semiconductor memory system 100. Referring to FIG. 1, the semiconductor memory system 100 includes memory controller 110 and memory module 120. Although FIG. 1 illustrates that the semiconductor memory system 100 has one memory module for convenience of explanation, two or more memory modules may be included in the semiconductor memory system 100.
Signals are exchanged between the memory controller 110 and the memory module 120 via various system buses included in the semiconductor memory system 100. For example, the memory controller 110 transmits write data to the memory module 120 or receives read data from the memory module 120 via data bus DQBUS. The memory controller 110 transmits command/address signals to the memory module 120 via command/address bus CABUS. In order to prevent such signals from becoming distorted due to impedance mismatching, multiple termination resistors RT11 and RT12 may be respectively connected to ends of the data bus DQBUS and the command/address bus CABUS. The memory controller 110, the memory module 120 and the termination resistors RT11 and RT12 are disposed on a motherboard in the semiconductor memory system 100.
At least one semiconductor memory device may be mounted in the memory module 120. For example, first through nth semiconductor memory devices DRAM1 to DRAMn may be mounted in the memory module 120. Each of the first through nth semiconductor memory devices DRAM1 to DRAMn may include data output buffer 121, data input buffer 122 and command/address input buffer 123. Also, the memory module 120 may further include command/address buffer 124 that temporarily stores the command/address signal received from the memory controller 110. The command/address buffer 124 is commonly used by the first through nth semiconductor memory devices DRAM1 to DRAMn, and buffers the command/address signals received from the memory controller 110 and provides a result of the buffering to the first through nth semiconductor memory devices DRAM1 to DRAMn.
In general, pseudo-differential signaling may be used to receive data or a command/address signal from DDR SDRAM. According to pseudo-differential signaling, the data input buffer 122 receives input data and a reference voltage VrefDQ for data, and generates internal input data DIN by amplifying a voltage difference between the input data and the reference voltage VrefDQ. Also, the command/address input buffer 123 receives the command/address signal and a reference voltage VrefCA for a command/address signal, and generates an internal command/address signal CAI by amplifying a voltage difference between the input data and the reference voltage VrefCA. The memory controller 110 may provide the input data and the command/address signal via a system bus.
The reference voltage VrefDQ for data and the reference voltage VrefCA for a command/address may be applied by the memory controller 110 or may be generated from a predetermined power supply voltage in the memory module 120. If these reference voltages are applied via a system bus, noise may occur in the reference voltage VrefCA applied to the command/address input buffer 124 when the data output buffer 121, for example, operates. In order to reduce such noise, a bus for transmitting the reference voltage VrefDQ for data (e.g., Vref DQBUS) and a bus for transmitting the reference voltage VrefCA for a command/address (e.g., Vref CABUS) are separately provided.
DDR semiconductor memory devices, such as DDR2 SDRAM and DDR3 SDRAM, have been developed for increasing operating speeds and decreasing driving voltages. To secure the integrity of signals exchanged between the memory controller 110 and the memory module 120 in the memory system 100, a termination device is generally used. Conventionally, a general termination resistor is connected to a system bus, such as the data bus DQBUS or the command/address bus CABUS, on a motherboard or an additional termination resistor (not shown) is simply disposed in a semiconductor memory device. The termination device is disposed regardless of the reference voltage VrefDQ for data, which is applied to the data input buffer 122, and regardless of the reference voltage VrefCA for a command/address signal, which is applied to the command/address input buffer 124. Such a conventional method may be applied to DDR3 SDRAM and a semiconductor memory system which is developed prior to DDR3 SDRAM, in terms of signal integrity.
However, for memory systems employing semiconductor memory devices developed after DDR3 SDRAM, for example, the data transmission rate is higher and a driving voltage is lower than DDR3 SDRAM. Thus, securing signal integrity is limited simply using such a conventional method. Therefore, there is a growing need to develop a method of securing signal integrity for a memory system using semiconductor memory devices developed after development of DDR3 SDRAM.